III-V compound semiconductor materials include elements from the third group (such as Al, Ga, and In) and fifth group (such as N, P, As, and Sb) of the periodic table. The III-V compound semiconductor materials are commonly used in high-speed transistors and in optoelectronic devices. III-V fabrications are more expensive than silicon fabrications. The semiconductor industry has therefore sought to combine the high-speed III-V semiconductors as both electronic and optoelectronic devices with low-cost Si circuitry.
Integration of III-V functional devices on Si substrates has been achieved by epitaxial growth of III-V material layers on Si. See, Yonezu, Hiroo, “Control of structural defects in group III-V-N alloys grown on Si,” Semiconductor science and technology 17.8: 762 (2002). Integration has also been achieved by directly bonding of III-V semiconductor layers with a Si wafer. Grupen-Shemansky, et al., U.S. Pat. No. 5,346,848 (Method of bonding silicon and III-V semiconductor materials) discloses a method that uses a semiconductor interlayer formed on the III-V material prior to bonding to a silicon wafer. The interlayer is silicon dioxide, doped silicon dioxide, silicon nitride, polysilicon, or amorphous silicon. The III-V layer is thinned after bonding to relieve stress. In this method, the interlayers (dielectric layers deposited on both III-V surface and Si side) are brought together to form bond through van der Waals' forces, which often require high annealing temperatures for activation. This method provides temperatures as low as 200° C. This process is a form of direct wafer bonding process that requires extreme cleanness and flatness of the bonding interface (and in some cases elevated bonding temperature beyond 200° C.). These bonding approaches tend to have low yields, especially for large area bonding beyond 1×1 cm2. Additionally, during cooling, the mismatch in the thermal expansion coefficients can lead to defects in the III-V device layer. The strength of bonds achieved at lower temperatures of 200° C. may also be lower than when higher temperatures are used. Generally, artisans use higher temperatures in the direct bonding processes to ensure bond strength. Bothra U.S. Pat. No. 6,030,884 (Hexagonal semiconductor die, semiconductor substrates, and methods of forming a semiconductor die) discloses use of a strained semiconductor layer between the silicon layer and the III-V group compound semiconductor layer prior to high temperature (>450° C.) heat treatment for bonding. Strained semiconductor layers attempt to compensate for direct bonding problems, and the high temperature is poorly suited for CMOS processes in general, and is at the onset of decomposition of most III-V compound semiconductors. Czornomaz, L., et al. “An integration path for gate-first UTB III-V-on-insulator MOSFETs with silicon, using direct wafer bonding and donor wafer recycling.” Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE (2012), discloses transfer of high-quality InGaAs/InAlAs heterostructures (tch<10 nm) by direct wafer bonding and hydrogen-induced thermal splitting. This is also a high temperature process that makes use of a dielectric interlayer to achieve direct wafer bonding. The donor wafer that provided the III-V heterostructures can be recycled to reduce cost.
With such conventional epitaxial growth processes, the heteroepitaxial growth of III-V semiconductors on a Si surface is hampered by the high density of crystal defects in the grown III-V layer, which is caused by the large difference in the lattice constant between the III-V materials and Si (lattice mismatch, generally >5%). This approach is not compatible with CMOS fabrication processes due to the high temperature required to epitaxially grow the III-V material on Si.
Such conventional bonding processes for of III-V semiconductors onto Si wafers generally require a heat treatment at elevated temperature to induce atomic re-arrangements at the intimately touched interface for secure bonding. The sample surfaces need to be treated to achieve a total surface roughness less than 1 nm to activate bonding. This high temperature heat treatment and subsequent cooling stage may introduce a large thermal stress and subsequent crystal defects in the III-V semiconductor layer.
Other bonding methods have been proposed to meet different requirements of device fabrication. This include epitaxial transfer (Ko, Hyunhyub, et al. “Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors.” Nature 468.7321 286-289 (2010)), eutectic bonding (Wolffenbuttel, R. F., and K. D. Wise. “Low-temperature silicon wafer-to-wafer bonding using gold at eutectic temperature.” Sensors and Actuators A: Physical 43.1 223-229 (1994), and adhesive bonding (Niklaus, Frank, et al. “Adhesive wafer bonding.” Journal of applied physics 99.3 031101 (2006)). These methods are not typically compatible with CMOS process due to complicated procedures, or due to strong changes to the surface morphology of bonding layer. The Wolffenbuttel method, for example, involves heating to temperature higher than Au—Si eutectic point (melting temperature of Au—Si alloy), which is not preferable for an industrial CMOS process. Alloys with Au are also not CMOS compatible. Melting introduces a liquid phase, which introduces the possibility of damage to device geometries or structures.
For example, the eutectic bonding process of Wolffenbuttel and Wise involves dissolution of Si to form a liquid phase. This dissolution and the required Au are not desired in a CMOS compatible process, and can fail to provide for electrical isolation between the metal and semiconductor. The Ko et al. process patterns InAs films with PMMA nanoribbons, wet etches an underling AlGaSB layer and transfers the InAs nanoribbons to silicon/silicon dioxide substrates with an elastomeric PDMS slab. The etching, polymer materials and transfers and not easily adapted to CMOS processing, and the shape of structures that can be formed is limited to the nanoribbon shape. The Frank adhesive process identifies polymers that are suitable for adhesive wafer bonding. Adhesive bonding may prevent long-term stability of device operations, causing problems with polymer ageing, device heat dissipation, etc. Bahl, U.S. Pat. No. 7,608,471 discloses a process to transfer III-V structures separated from each other by score lines extending through a separation layer to a sapphire substrate. The structures are aligned with bonding pads on a silicon substrate and are fused to the pads. A laser is used to decompose separation layers and removing portions of the III-V wafer that are not fused, which concludes a complex process that is not generally compatible with CMOS fabrication and limits shapes of the fabrications. Generally, these methods don't allow the integration of arbitrary-shaped device layers to desired locations on a CMOS circuit freely.